| COMPUTER
SYSTEM ARCHITECTURE |
Artificial Intelligence
[1] G.S. Almasi
and A. Gottlieb, Dependency graphs and analysis, in "Highly
Parallel Computing", Bejamin/Cummings Publishing Company, 2nd ed.,
1994, pp. 309-314.
[2] G.S. Almasi and A. Gottlieb, Kendall Square Research KSRI, in "Highly Parallel Computing", Bejamins/Cummings Publishing Company, 2nd ed., 1994, pp. 549-553.
[3] Arvind, L. Bic, and T. Ungerer, Evolution of dataflow computers, in "Advanced Topics in Data-Flow Computing", Prentice-Hall, Englewood Cliffs, 1991.
[4] J.C. Bezdek, What is computational intelligence?, in "Computational Intelligence: Imitating Life", IEEE Press, 1994, pp. 1-12.
[5] D.E. Culler, S.C. Goldstein, K.E. Schauser, and T. von Eicken, TAM – A compiler controlled Threaded Abstract Machine, "Journal of Parallel and Distributed Computing, Special Issue on Dataflow", 1993.
[6] J.B. Dennis, First version of a data flow procedure language, in "Lecture Notes in Computer Science", vol. 19, Springer-Verlag, Berlin, 1974.
[7] S.C. Goldstein, K.E. Schauser, and D. Culler, Enabling primitives for compiling parallel languages, in "Languages, Compilers and Run-Time Systems for Scalable Systems", Kuver Academic Press, 1996, pp. 153-168.
[8] E. Hagersten, A. Landin, and S. Haridi, DDM – A Cache-Only Memory Architecture, "IEEE Computer", 25/9, 1992.
[9] J. Hennessey and D. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers Inc., 1990.
[10] F. Henritzi, A. Bleck, R. Moore, B. Klaurer, and K. Waldschmidt, ADARC: A new multi-instruction issue approach, in "International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA ’96)", 1996.
[11] H. Hertz, A. Krogh, and R.G. Palmer, Introduction, in "Introduction to the Theory of Neural Computation", ch. 1, Addison-Welsey, 1991, p. 10.
[12] J.H. Holland, Adaptation in Natural and Artificial Systems, University of Michigan Press, 1975.
[13] B. Klauer, J. Strohschneider, F. Henritzi, S. Zickenheimer, and K. Waldschmidt, Computation of neural structures on dataflow computers, in "EUROMICRO ‘95", Como, 1995.
[14] T.G. Lewis and H. El-Rewini, Scheduling parallel programs, in "Introduction to Parallel Computing", ch. 9, Prentice-Hall, Englewood Cliffs, 1992, pp. 245-281.
[15] C. Mead (ed.), Analog VLSI and Neural Systems, Addison-Wesley, 1989.
[16] R.S. Nikhil, A multithreaded implementation of Id using P-RISC graphs, in "Proceedings of the Sixth Annual Workshop on Languages and Compilers for Parallel Computing", Springer-Verlag, Berlin, 1993, pp. 390-405.
[17] D.E. Rumelhart, G.E. Hinton, and R.J. Williams, Learning internal representations by error propagation, in "Parallel Distributed Processing", ch. 8, 1986, pp. 318-364.
[18] D.E. Rumelhart and J.L. McClelland, PDP Models and general issues in cognitive science, in "Parallel Distributed Processing", ch. 4, 1986, pp. 110-146.
[19] D.E. Rumelhart, J.L. McClelland, and the PDP Research Group (eds.), Parallel Distributed Processing: Explorations in the Microstructure of Cognition, vol. I: Foundations, MIT Press, 1986.
[20] S.G. Shiva, Neural networks, in "Pipelined and Parallel Computer Architectures", sect. 8.3.1., HarperCollins Publishers, 1996. pp. 243-247.
[21] E.S. Sinencio and R.W. Newcomb (eds.), IEEE Transactions on Neural Networks: Special Issue on Neural Network Hardware, vol. 4, 1993.
[22] J. Strohschneider and B. Klauer, and K. Waldschmidt, Concept for an associative dataflow architecture, in "2nd Associative Processing and Applications Workshop", 1993.
[23] T. von Eicken, D.E. Culler, S.C. Goldstein, and K.E. Schauser, Active messages: a mechanism for integrated communication and computation, in "Proceedings of the 19th International Symposium on Computer Architecture", Gold Coast, 1992.
[24] J.M. Zurada, R.J. Marks, and C.J. Robinson (eds.), Computational Intelligence: Imitating Life, IEEE Press, 1994.
[25] J.M. Zurada, R.J. Marks, and C.J. Robinson (eds.), Introduction, in "Computational Intelligence: Imitating Life", IEEE Press, 1994, pp. v-xi.
[2] G.S. Almasi and A. Gottlieb, Kendall Square Research KSRI, in "Highly Parallel Computing", Bejamins/Cummings Publishing Company, 2nd ed., 1994, pp. 549-553.
[3] Arvind, L. Bic, and T. Ungerer, Evolution of dataflow computers, in "Advanced Topics in Data-Flow Computing", Prentice-Hall, Englewood Cliffs, 1991.
[4] J.C. Bezdek, What is computational intelligence?, in "Computational Intelligence: Imitating Life", IEEE Press, 1994, pp. 1-12.
[5] D.E. Culler, S.C. Goldstein, K.E. Schauser, and T. von Eicken, TAM – A compiler controlled Threaded Abstract Machine, "Journal of Parallel and Distributed Computing, Special Issue on Dataflow", 1993.
[6] J.B. Dennis, First version of a data flow procedure language, in "Lecture Notes in Computer Science", vol. 19, Springer-Verlag, Berlin, 1974.
[7] S.C. Goldstein, K.E. Schauser, and D. Culler, Enabling primitives for compiling parallel languages, in "Languages, Compilers and Run-Time Systems for Scalable Systems", Kuver Academic Press, 1996, pp. 153-168.
[8] E. Hagersten, A. Landin, and S. Haridi, DDM – A Cache-Only Memory Architecture, "IEEE Computer", 25/9, 1992.
[9] J. Hennessey and D. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers Inc., 1990.
[10] F. Henritzi, A. Bleck, R. Moore, B. Klaurer, and K. Waldschmidt, ADARC: A new multi-instruction issue approach, in "International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA ’96)", 1996.
[11] H. Hertz, A. Krogh, and R.G. Palmer, Introduction, in "Introduction to the Theory of Neural Computation", ch. 1, Addison-Welsey, 1991, p. 10.
[12] J.H. Holland, Adaptation in Natural and Artificial Systems, University of Michigan Press, 1975.
[13] B. Klauer, J. Strohschneider, F. Henritzi, S. Zickenheimer, and K. Waldschmidt, Computation of neural structures on dataflow computers, in "EUROMICRO ‘95", Como, 1995.
[14] T.G. Lewis and H. El-Rewini, Scheduling parallel programs, in "Introduction to Parallel Computing", ch. 9, Prentice-Hall, Englewood Cliffs, 1992, pp. 245-281.
[15] C. Mead (ed.), Analog VLSI and Neural Systems, Addison-Wesley, 1989.
[16] R.S. Nikhil, A multithreaded implementation of Id using P-RISC graphs, in "Proceedings of the Sixth Annual Workshop on Languages and Compilers for Parallel Computing", Springer-Verlag, Berlin, 1993, pp. 390-405.
[17] D.E. Rumelhart, G.E. Hinton, and R.J. Williams, Learning internal representations by error propagation, in "Parallel Distributed Processing", ch. 8, 1986, pp. 318-364.
[18] D.E. Rumelhart and J.L. McClelland, PDP Models and general issues in cognitive science, in "Parallel Distributed Processing", ch. 4, 1986, pp. 110-146.
[19] D.E. Rumelhart, J.L. McClelland, and the PDP Research Group (eds.), Parallel Distributed Processing: Explorations in the Microstructure of Cognition, vol. I: Foundations, MIT Press, 1986.
[20] S.G. Shiva, Neural networks, in "Pipelined and Parallel Computer Architectures", sect. 8.3.1., HarperCollins Publishers, 1996. pp. 243-247.
[21] E.S. Sinencio and R.W. Newcomb (eds.), IEEE Transactions on Neural Networks: Special Issue on Neural Network Hardware, vol. 4, 1993.
[22] J. Strohschneider and B. Klauer, and K. Waldschmidt, Concept for an associative dataflow architecture, in "2nd Associative Processing and Applications Workshop", 1993.
[23] T. von Eicken, D.E. Culler, S.C. Goldstein, and K.E. Schauser, Active messages: a mechanism for integrated communication and computation, in "Proceedings of the 19th International Symposium on Computer Architecture", Gold Coast, 1992.
[24] J.M. Zurada, R.J. Marks, and C.J. Robinson (eds.), Computational Intelligence: Imitating Life, IEEE Press, 1994.
[25] J.M. Zurada, R.J. Marks, and C.J. Robinson (eds.), Introduction, in "Computational Intelligence: Imitating Life", IEEE Press, 1994, pp. v-xi.
