| COMPUTER
SYSTEM ARCHITECTURE |
Performance Evaluation Aspects of Computer System
[1] G.B. Adams,
D.P. Agrawal, and H.J. Siegel, A Survey and Comparison of Fault-Tolerant
Multistage Interconnection Networks, "IEEE Computers", 1987,
pp. 14-27.
[2] G.B. Adams and H.J. Siegel, Modifications to Improve the Fault-Tolerance of the Extra Stage Cube Interconnection Network, in "Proceedings of the International Conference Parallel Processing", 1984, pp. 169-173.
[3] S.B. Akers and B. Krishnamurthy, A group-theoretic model for symmetric interconnection networks, "IEEE Transactions on Computer", 38/4, 1989, pp. 555-566.
[4] J. Arlat, K. Kanoun, and J.C. Lapric, Dependability Modelling and Evaluation of Software Fault Tolerant Systems, "IEEE Transactions on Computers", 39/4, 1990, pp. 504-512.
[5] A. Avizienis, Fault Tolerance: The Survival Attribute of Digital Systems, in "Proceedings of IEEE", 66/10, 1978, pp. 1109-1125.
[6] A. Avizienis, The N-Version Approach to Fault-Tolerant Software, "IEEE Transactions on Software Engineering", 11/12, 1985, pp. 1491-1501.
[7] C. Chen, D.P. Agrawal, and J.R. Burke, dBCube: a new class of hierarchical multiprocessor interconnection networks with area efficient layout, "IEEE Transactions on Parallel and Distributed Systems", 4/12, 1993, pp. 1332-1344.
[8] E. Ganesan and D.K. Pradhari, The hyper-deBruijn networks: scalable versatile architecture, "IEEE Transactions on Parallel and Distributed Systems", 4/9, 1993, pp. 962-978.
[9] A.L. Geol and K. Okumoto, Time-Dependent Error-Detection Rate Models for Software Reliability and Other Performance measures, "IEEE Transactions on Reliability", 28/3, 1979, pp. 206-211.
[10] A. Itoh, A Fault-Tolerant Switching Architecture for ATM Networks, in "IEEE International Conference on Communications", 3, 1992, pp. 1639-1645.
[11] K. Kanoun, M. Kaaniche, C. Beounes, J.C. Lapric, and J. Arlat, Reliability Growth of Fault-Tolerant Software, "IEEE Transactions on Reliability", 42/2, 1979, pp. 205-219.
[12] K.H. Kim and H.O. Welch, Distributed Execution of Recovery Blocks: An Approach for Uniform Treatment of Hardware and Software Faults in Real-Time Applications, "IEEE Transactions on Computers", 38/5, 1989, pp. 626-636.
[13] V.P. Kumar and A.L. Reibman, Failure Dependent Performance Analysis of a Fault-Tolerant on Fault-Tolerant Multistage Interconnection Networks, "IEEE Transactions on Computers", 38/12, 1989, pp. 1703-1713.
[14] J.C. Lapric, J. Arlat, C. Beounes, and K. Kanoun, Definition and Analysis of Hardware and Software-Fault-Tolerant Architectures, "IEEE Computer", 23, 1990, pp. 39-51.
[15] F.T. Leighton, Introductions to Parallel Algorithms and Architectures: Arrays, Trees and Hypercubes, Morgan Kaufman, 1992.
[16] R.J. McMillen, A Survey of Interconnection Networks "IEEE Globecom", 84, 1984, pp. 105-113.
[17] K. Padmanabham and D.H. Lawrie, A Class of Redundant Path Multistage Interconnection Networks, "IEEE Transactions on Computers, 32/12, 1983, pp. 1099-1108.
[18] B. Randell, System Structure for Software Fault Tolerance, "IEEE Transactions on Software Engineering", 1/2, 1975, pp. 220-232.
[19] E.P. Rathgeb, T.H. Theimer, and M.N. Huber, ATM Switches – Basic Architecture and Their Performance, "Journal of Digital and Analog Cabled Systems", 2, 1989, pp. 227-236.
[20] S.M. Reddy and V.P. Kumar, On Fault-Tolerant Multistage Interconnection Networks, in "Proceedings of the International Conference Parallel Processing", 1984, pp. 155-164.
[21] Y. Saad and M.H. Shuitz, Topological properties of hypercubes, "IEEE Transactions on Computers", 37/7, 1988, pp. 867-872.
[22] F.A. Tobagi, Fast Packet Switch Architecture for Broadband Integrated Services Digital Networks, in "Proceedings of the IEEE", vol. 78, n. 1, 1990, pp. 133-166.
[23] K.S. Trivedi, Probability and Statistics with Reliability Queuing and Computer Science Applications, Prentice-Hall, Englewood Cliffs, 1982.
[24] N. Tzeng, P. Yew, and C. Zhu, A Fault-Tolerant Scheme for On Fault-Tolerant Multistage Interconnection Networks, in "12th International Symposium on Computer Architecture", 1985, pp. 368-375.
[25] P. Vadapalli and P.K. Srimani, A new family of Cayley graph interconnection networks of constant degree four, "IEEE Transactions on Parallel and Distributed Systems", 7/1, 1996.
[26] P. Vadapalli and P.K. Srimani, Fault tolerant ring embedding in tetravalent Cayley networks graphs, "Journal of Circuits, Systems and Computers", 6/5, 1996, pp. 527-536.
[27] C. Wu and T. Feng, On a Class of Multistage Interconnection Networks, "IEEE Transaction on Computers", 29/8, 1980, pp. 694-702.
[2] G.B. Adams and H.J. Siegel, Modifications to Improve the Fault-Tolerance of the Extra Stage Cube Interconnection Network, in "Proceedings of the International Conference Parallel Processing", 1984, pp. 169-173.
[3] S.B. Akers and B. Krishnamurthy, A group-theoretic model for symmetric interconnection networks, "IEEE Transactions on Computer", 38/4, 1989, pp. 555-566.
[4] J. Arlat, K. Kanoun, and J.C. Lapric, Dependability Modelling and Evaluation of Software Fault Tolerant Systems, "IEEE Transactions on Computers", 39/4, 1990, pp. 504-512.
[5] A. Avizienis, Fault Tolerance: The Survival Attribute of Digital Systems, in "Proceedings of IEEE", 66/10, 1978, pp. 1109-1125.
[6] A. Avizienis, The N-Version Approach to Fault-Tolerant Software, "IEEE Transactions on Software Engineering", 11/12, 1985, pp. 1491-1501.
[7] C. Chen, D.P. Agrawal, and J.R. Burke, dBCube: a new class of hierarchical multiprocessor interconnection networks with area efficient layout, "IEEE Transactions on Parallel and Distributed Systems", 4/12, 1993, pp. 1332-1344.
[8] E. Ganesan and D.K. Pradhari, The hyper-deBruijn networks: scalable versatile architecture, "IEEE Transactions on Parallel and Distributed Systems", 4/9, 1993, pp. 962-978.
[9] A.L. Geol and K. Okumoto, Time-Dependent Error-Detection Rate Models for Software Reliability and Other Performance measures, "IEEE Transactions on Reliability", 28/3, 1979, pp. 206-211.
[10] A. Itoh, A Fault-Tolerant Switching Architecture for ATM Networks, in "IEEE International Conference on Communications", 3, 1992, pp. 1639-1645.
[11] K. Kanoun, M. Kaaniche, C. Beounes, J.C. Lapric, and J. Arlat, Reliability Growth of Fault-Tolerant Software, "IEEE Transactions on Reliability", 42/2, 1979, pp. 205-219.
[12] K.H. Kim and H.O. Welch, Distributed Execution of Recovery Blocks: An Approach for Uniform Treatment of Hardware and Software Faults in Real-Time Applications, "IEEE Transactions on Computers", 38/5, 1989, pp. 626-636.
[13] V.P. Kumar and A.L. Reibman, Failure Dependent Performance Analysis of a Fault-Tolerant on Fault-Tolerant Multistage Interconnection Networks, "IEEE Transactions on Computers", 38/12, 1989, pp. 1703-1713.
[14] J.C. Lapric, J. Arlat, C. Beounes, and K. Kanoun, Definition and Analysis of Hardware and Software-Fault-Tolerant Architectures, "IEEE Computer", 23, 1990, pp. 39-51.
[15] F.T. Leighton, Introductions to Parallel Algorithms and Architectures: Arrays, Trees and Hypercubes, Morgan Kaufman, 1992.
[16] R.J. McMillen, A Survey of Interconnection Networks "IEEE Globecom", 84, 1984, pp. 105-113.
[17] K. Padmanabham and D.H. Lawrie, A Class of Redundant Path Multistage Interconnection Networks, "IEEE Transactions on Computers, 32/12, 1983, pp. 1099-1108.
[18] B. Randell, System Structure for Software Fault Tolerance, "IEEE Transactions on Software Engineering", 1/2, 1975, pp. 220-232.
[19] E.P. Rathgeb, T.H. Theimer, and M.N. Huber, ATM Switches – Basic Architecture and Their Performance, "Journal of Digital and Analog Cabled Systems", 2, 1989, pp. 227-236.
[20] S.M. Reddy and V.P. Kumar, On Fault-Tolerant Multistage Interconnection Networks, in "Proceedings of the International Conference Parallel Processing", 1984, pp. 155-164.
[21] Y. Saad and M.H. Shuitz, Topological properties of hypercubes, "IEEE Transactions on Computers", 37/7, 1988, pp. 867-872.
[22] F.A. Tobagi, Fast Packet Switch Architecture for Broadband Integrated Services Digital Networks, in "Proceedings of the IEEE", vol. 78, n. 1, 1990, pp. 133-166.
[23] K.S. Trivedi, Probability and Statistics with Reliability Queuing and Computer Science Applications, Prentice-Hall, Englewood Cliffs, 1982.
[24] N. Tzeng, P. Yew, and C. Zhu, A Fault-Tolerant Scheme for On Fault-Tolerant Multistage Interconnection Networks, in "12th International Symposium on Computer Architecture", 1985, pp. 368-375.
[25] P. Vadapalli and P.K. Srimani, A new family of Cayley graph interconnection networks of constant degree four, "IEEE Transactions on Parallel and Distributed Systems", 7/1, 1996.
[26] P. Vadapalli and P.K. Srimani, Fault tolerant ring embedding in tetravalent Cayley networks graphs, "Journal of Circuits, Systems and Computers", 6/5, 1996, pp. 527-536.
[27] C. Wu and T. Feng, On a Class of Multistage Interconnection Networks, "IEEE Transaction on Computers", 29/8, 1980, pp. 694-702.
