There is a need to do the simulation of this model on different processor models. An experiment was conducted to carried out to implement the same model on different processors such as Cray etc. Incidentally, they have showed deviation of performance of 25% to 100%. The prediction could be made only for BPRAM model. The message passing architecture for parallel processing is picking up importance. The general observation is to discourage models for this type of experiments.
This is another research area to develop the simulation environment for highly parallel architecture building. There is an acute need for simulation studies though. In this particular case, the multilevel cache performance models also need further research, because this is an important aspect with the present day technology.
